The job, in the employer's words
About IonQ:
IonQ, Inc. [NYSE: IONQ] is the world’s leading quantum platform and merchant supplier - delivering integrated quantum solutions across computing, networking, sensing, and security. IonQ’s newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting-edge systems that have been helping customers and partners including Amazon Web Services, and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense. In 2025, the company achieved 99.99% two-qubit gate fidelity, setting a world record in quantum computing performance.
Headquartered in College Park, Maryland, IonQ has operations in California, Colorado, Massachusetts, Tennessee, Washington, Italy, South Korea, Sweden, Switzerland, Canada, and the United Kingdom. Our quantum computing services are available through all major cloud providers, while we also meet the needs of networking and sensing customers across land, sea, air, and space. IonQ is making quantum platforms more accessible and impactful than ever before.
We are seeking a Quantum Design Enablement Engineer to join our Manufacturing team in our mission to build the world’s best quantum computers. In this role, you will serve as the primary technical interface between internal quantum chip designers and external foundry partners, playing a key role in bringing next-generation trapped-ion hardware to life.
You will ensure our quantum chip designs transition seamlessly into reliable, scalable fabrication. Core responsibilities include managing the tapeout flow, executing physical verification, performing hands-on layout for test structures and reticle assembly, and partnering with foundries to refine our Process Design Kit (PDK).
Key Responsibilities
- Foundry Interface & PDK Management: Serve as the primary technical point of contact with external foundry partners. Work collaboratively to define, implement, and troubleshoot the PDK, ensuring it accurately reflects foundry capabilities and constraints.
- Tapeout & Mask Validation: Own the tapeout process. Perform comprehensive mask layout validation, execute physical verification (DRC/LVS), and ensure final GDSII/OASIS files are fully compliant with foundry requirements before handoff.
- Design Team Enablement: Act as a liaison between manufacturing and core product design teams. Translate complex foundry requirements and process updates into clear design rules and best practices for design engineers.
- Layout & Integration: Perform hands-on layout modifications, frame generation, and reticle assembly as needed to finalize masks for manufacturing. Generate custom layouts for test structures, process monitos, or simple test chips when necessary.
- Rule Deck Customization: Work primarily with foundry-provided DRC/LVS rule decks while taking the initiative to write, modify, and optimize custom internal rule checks for specialized trapped-ion quantum computer design constraints.
- Continuous Improvement: Analyze tapeout data and foundry feedback to proactively drive improvements in the PDK, design rules, and overall design-to-manufacturing workflow.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Physics, Materials Science, or a related technical field.
- 3 - 5 years of industry experience in semiconductor manufacturing, design enablement, tapeout operations, or a closely related field.
- Hands-on experience with physical verification tools (such as Siemens Calibre, Cadence Pegasus, or Synopsys IC Validator) and running standard DRC, LVS, and ERC checks.
- Proficiency with standard layout and viewing tools like Cadence Virtuoso or KLayout, including the ability to perform layout edits and detailed mask reviews.
- Strong understanding of PDK architecture and technology files, as well as how foundry design rules dictate layout methodologies.
- Exceptional cross-functional communication skills, with demonstrated ability to negotiate technical requirements between external fab engineers and internal design teams.
Preferred Qualifications
- Strong proficiency in Python and hands-on experience with Python-based layout generation frameworks (such as gdsfactory, gdspy or the KLayout), alongside version control using Git.
- Experience with non-traditional semiconductor and microfabrication technologies, such as integrated photonics, MEMS, or specialized BEOL metallization.
- Experience writing or modifying custom physical verification rules (such as Calibre SVRF/TVF or equivalent) to develop layout rules specific to trapped-ion quantum computing hardware.
- Familiarity with standard CMOS device modeling principles and compact modeling methodologies.
- Understanding of Parasitic Extraction (PEX) flows and tools, with an awareness of how physical layout impacts parasitic capacitances, RF performance, and device behavior.
Location: This role is hybrid/onsite in College Park, MD location.
Travel: Up to 10%
Job ID: 1303
The approximate base salary range for this position is $126,887 - $166,127. The total compensation package includes base, bonus, and equity.
If this role has a commission structure, the compensation range below just reflects the base compensation range.
Compensation will vary based on individual factors such as education, qualifications, and experience of the final candidate(s), specific office location, and calibration against relevant market data and internal team equity. Posted base salary figures are subject to change as new market data becomes available. Our benefits include comprehensive medical, dental, and vision plans, matching 401(k), unlimited PTO and paid holidays, parental/adoption leave, legal insurance, and a home technology stipend. Details of participation in these benefit plans will be provided when a candidate receives an offer of employment.
At IonQ, we believe in fair treatment, access, opportunity, and advancement for all while striving to identify and eliminate barriers. We empower employees to thrive by fostering a culture of autonomy, productivity, and respect. We are dedicated to creating an environment where individuals can feel welcomed, respected, supported, and valued.
We are committed to equity and justice. We welcome different voices and viewpoints and do not discriminate on the basis of race, religion, ancestry, physical and/or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, transgender status, age, sexual orientation, military or veteran status, or any other basis protected by law. We are proud to be an Equal Employment Opportunity employer.
US Technical Jobs. The position you are applying for will require access to technology that is subject to U.S. export control and government contract restrictions. Employment with IonQ is contingent on either verifying “U.S. Person” (e.g., U.S. citizen, U.S. national, U.S. permanent resident, or lawfully admitted into the U.S. as a refugee or granted asylum) status for export controls and government contracts work, obtaining any necessary license, and/or confirming the availability of a license exception under U.S. export controls. Please note that in the absence of confirming you are a U.S. Person for export control and government contracts work purposes, IonQ may choose not to apply for a license or decline to use a license exception (if available) for you to access export-controlled technology that may require authorization, and similarly, you may not qualify for government contracts work that requires U.S. Persons, and IonQ may decline to proceed with your application on those bases alone. Accordingly, we will have some additional questions regarding your immigration status that will be used for export control and compliance purposes, and the answers will be reviewed by compliance personnel to ensure compliance with federal law.
US Non-Technical Jobs. Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Accordingly, we will have some additional questions regarding your immigration status that will be used for export control and compliance purposes, and the answers will be reviewed by compliance personnel to ensure compliance with federal law.
If you are interested in being a part of our team and mission, we encourage you to apply!
Requirements mentioned
- Bachelor’s or Master’s degree in Electrical Engineering, Physics, Materials Science, or a related technical field.
- 3 - 5 years of industry experience in semiconductor manufacturing, design enablement, tapeout operations, or a closely related field.
- Hands-on experience with physical verification tools (such as Siemens Calibre, Cadence Pegasus, or Synopsys IC Validator) and running standard DRC, LVS, and ERC checks.
- Proficiency with standard layout and viewing tools like Cadence Virtuoso or KLayout, including the ability to perform layout edits and detailed mask reviews.
- Strong understanding of PDK architecture and technology files, as well as how foundry design rules dictate layout methodologies.
- Exceptional cross-functional communication skills, with demonstrated ability to negotiate technical requirements between external fab engineers and internal design teams.
- Strong proficiency in Python and hands-on experience with Python-based layout generation frameworks (such as gdsfactory, gdspy or the KLayout), alongside version control using Git.
- Experience with non-traditional semiconductor and microfabrication technologies, such as integrated photonics, MEMS, or specialized BEOL metallization.
- Experience writing or modifying custom physical verification rules (such as Calibre SVRF/TVF or equivalent) to develop layout rules specific to trapped-ion quantum computing hardware.
- Familiarity with standard CMOS device modeling principles and compact modeling methodologies.
- Understanding of Parasitic Extraction (PEX) flows and tools, with an awareness of how physical layout impacts parasitic capacitances, RF performance, and device behavior.
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